The present invention relates to solid-state imaging devices, and in particular, to a CCD type solid-state imaging device.
As a CCD (Charge Coupled Device) type solid-state imaging device, a two-dimensional image sensor 180 as shown in, for example, FIG. 7 is known (refer to, for example, JP 2002-76319 A). The two-dimensional image sensor 180 has plural vertical CCD's 102 and plural light-receiving portions (photodiodes) 101 arranged at a prescribed pitch PV along the vertical CCD's 102 in a rectangular imaging area 108 set on a semiconductor substrate. The vertical CCD's 102 extend in the vertical direction (vertical direction in FIG. 7) and are arranged at a prescribed pitch PH in the horizontal direction (transverse direction in FIG. 7). One end (lower end in FIG. 7) of each vertical CCD 102 is connected to a horizontal CCD 103 that extends in the horizontal detection. The reference numeral 104 denotes an amplifier. A group 105 of four-phase vertical transfer electrodes 105-1, 105-2, 105-3 and 105-4 constituted of polysilicon doped with an impurity is provided horizontally across the imaging area 108. Although only one group is shown in the figure for simplicity, plural groups identical to the group 105 are actually provided at the same pitch PV as that of the light-receiving portions 101.
Moreover, a group 106 of vertical transfer signal lines 106-1, 106-2, 106-3 and 106-4 is provided along three sides of the periphery of the imaging area 108. Vertical transfer signal input terminals 107-1, 107-2, 107-3 and 107-4, to which four-phase clock pulses φV1, φV2, φV3 and φV4 are inputted, are provided in portions along the upper side of the imaging area of the vertical transfer signal lines 106-1, 106-2, 106-3 and 106-4, respectively. The vertical transfer signal lines 106-1, 106-2, 106-3 and 106-4 connect the vertical transfer signal input terminals, to which the clock pulses φV1, φV2, φV3 and φV4 are inputted, with the end portions (located at the right and left of the imaging area 108) of the vertical transfer electrodes, to which the clock pulses are to be applied, in every phase of the clock pulse. The vertical transfer signal lines 106-1, 106-2, 106-3 and 106-4 are constituted of a mutually identical metal material and set to same width (i.e., W1=W2=W3=W4) and same thickness. It is noted that the lines have a portion (not shown) constituted of polysilicon to form a wiring portion for jumping other wiring lines, a protective resistance or the like.
In operation, the light-receiving portions 101 convert incident light into signal charges. The four-phase clock pulses φV1, φV2, φV3 and φV4 are applied to the vertical transfer signal input terminals 107-1, 107-2, 107-3 and 107-4 by an external circuit (not shown). The clock pulses φV1, φV2, φV3 and φV4 of the phases are transmitted to the end portions of the corresponding vertical transfer electrodes 105-1, 105-2, 105-3 and 105-4 from the corresponding vertical transfer signal input terminals 107-1, 107-2, 107-3 and 107-4, respectively, through the vertical transfer signal lines 106-1, 106-2, 106-3 and 106-4 connected to the input terminals. As a result, the signal charges generated by the light-receiving portions 101 are transferred in the vertical direction toward the horizontal CCD 103 through the vertical CCD's 102 adjacent to the light-receiving portions 101. The transferred signal charges are further transferred in the horizontal direction through the horizontal CCD 103 toward the amplifier 104, amplified by the amplifier 104 and then outputted.
Moreover, in recent years, digital still cameras having a large number of pixels and the like generally have a still mode in which the whole pixel information is read and a monitoring mode in which the information is read while reducing the amount of information by thinning, pixel addition or the like. FIG. 8 shows the construction of a CCD type two-dimensional image sensor 190 that is able to perform such thinning read. In FIG. 8, the same constituents as those of FIG. 7 are denoted by the same reference numerals.
In the two-dimensional image sensor 190, a group 115A of four-phase vertical transfer electrodes 115-1A, 115-2, 115-3 and 115-4, a group 115-1B of four-phase vertical transfer electrodes 115-1B, 115-2, 115-3 and 115-4 and a group 115-1C of four-phase vertical transfer electrodes 115-1C, 115-2, 115-3 and 115-4, which are constituted of polysilicon doped with an impurity, are provided horizontally across the imaging area 108. Although three groups are shown in the figure for simplicity, numbers of groups identical to the three groups 115A, 115B and 115C are actually provided in a repetitive pattern in the vertical direction.
The clock pulse φV1 of the first phase is divided into three clock pulses φV1A, φV1B and φV1C that are mutually independently selected and inputted. In accordance with the above, three vertical transfer signal input terminals 117A-1, 117B-1 and 117C-1 and three vertical transfer signal lines 116A-1, 116B-1 and 116C-1 are provided. The three vertical transfer signal lines 116A-1, 116B-1 and 116C-1 are distributed to plural groups 115A, 115B and 115C of the transfer electrodes arranged in the vertical direction and connected to the transfer electrodes 115-1A, 115-1B and 115-1C, respectively, to which the clock pulses φV1A, φV1B and φV1C of the first phase are to be sequentially applied. The other vertical transfer signal input terminals 117-2, 117-3 and 117-4 and the vertical transfer signal lines 116-2, 116-3 and 116-4 are the same as the vertical transfer signal input terminals 107-2, 107-3 and 107-4 and the vertical transfer signal lines 106-2, 106-3 and 106-4, respectively, in FIG. 7. The vertical transfer signal lines 116A-1, 116B-1, 116C-1, 116-2, 116-3 and 116-4 are constituted of a mutually identical metal material and set to same width (i.e., W1A=W1B=W1C=W2=W3=W4) and same thickness. It is noted that the lines have a portion (not shown) constituted of polysilicon to form a wiring portion for jumping other wiring lines, a protective resistance or the like.
The basic operation of the two-dimensional image sensor 190 is the same as that of the one of FIG. 7. When the signal charges generated by the light-receiving portions 101 are read to the vertical CCD's 102, it is possible to select between a manner such that the inputted clock pulses φV1A, φV1B and φV1C of the first phase do not simultaneously go High level but alternately go High level, a manner such that a certain clock pulse does not go High level and another manner, in order to perform the thinning read. When the signal charges are transferred through the vertical CCD's 102, all the clock pulses φV1A, φV1B and φV1C go High level or Low level at the same timing as φV1 and operate as the four-phase clock pulses φV1, φV2, φV3 and φV4.
Since the clock pulses φV1A, φV1B and φV1C are obtained by dividing the original clock pulse φV1 in order to perform the thinning read, the sum total of the number of the vertical transfer electrodes to which the clock pulses φV1A, φV1B and φV1C are applied and the number of the vertical transfer electrodes to which, for example, another clock pulses φV2 is applied are the same. Moreover, the number of the vertical transfer electrodes to which the clock pulse φV2 is applied, the number of the electrodes to which the clock pulse φV3 is applied and the number of the electrodes to which the clock pulse φV4 is applied are the same.
The load capacity of the transfer electrode (gate) is constituted of (1) a parasitic capacitance between gates, (2) a parasitic capacitance between each gate and a light-shielding film that exists above the gate, (3) a parasitic capacitance between each gate and a substrate that exists below the portion and so on. Since the surface area and the overlap area with other electrodes are varied depending on each transfer electrode, the load capacity possessed by each transfer electrode is also varied.
For example, FIG. 5 shows a plan layout of one group of vertical transfer electrodes 105-1, 105-2, 105-3 and 105-4 in the two-dimensional image sensor 180 shown in FIG. 7. FIG. 6 shows a sectional view taken along the line A–A′ in FIG. 5. The reference numeral 100 denotes a surface of the semiconductor substrate, and the numeral 109 denotes the light-shielding film. As is apparent from FIGS. 5 and 6, the surface area and the overlap area with other electrodes of the vertical transfer electrode 105-1 to which the clock pulse φV1 of the first phase is applied are larger than those of the vertical transfer electrodes 105-2, 105-3 and 105-4 of the other phases. In accordance with the above, the load capacity of the vertical transfer electrode 105-1 is larger than the load capacity of each of the other vertical transfer electrodes 105-2, 105-3 and 105-4. As a result, the time constant of the signal propagation system (including the vertical transfer signal input terminal to the vertical transfer electrode) of the clock pulse φV1 of the first phase is greater than the time constant of each of the signal propagation systems of the clock pulses φV2, φV3 and φV4 of the other phases.
Therefore, even if the clock pulses φV1, φV2, φV3 and φV4 are inputted in roughly rectangular waveforms to the vertical transfer signal input terminals 107-1, 107-2, 107-3 and 107-4, respectively, as shown in FIG. 9A, the waveform blunting of the clock pulse φV1 of the first phase becomes larger than the waveform blunting of the clock pulses φV2, φV3 and φV4 of the other phases in a center portion of the imaging area 108 as shown in FIG. 9B. In concrete, at a timing τ1 in FIG. 9B, the clock pulse φV4 starts to rise before the clock pulse φV1 sufficiently falls. Then, as shown in FIG. 10A, the potential barriers ψW1 and ψ4 that the vertical transfer electrodes 105-1 and 105-4 make in the vertical CCD's 102 become lower than the potential barriers ψ2 and ψ3 that the remaining vertical transfer electrodes 105-2 and 105-3 shown in FIG. 10B make. This consequently leads to a problem that the handling amount of charge of the vertical CCD's 102 is reduced due to the low potential barriers ψ1 and ψ4.
On the other hand, in the two-dimensional image sensor 190 of the type that is able to perform the thinning read shown in FIG. 8, the number of the vertical transfer electrodes to which the individual clock pulses of the first phase (e.g., φV1A) are applied is extremely smaller than the number of, for example, the vertical transfer electrodes to which the clock pulses φV2, φV3 and φV4 of the other phases are applied. As a result, the time constant of the signal propagation system of the individual clock pulses of the first phase (e.g., φV1A) is smaller than the time constant of each of the signal propagation systems of the clock pulses φV2, φV3 and φV4 of the other phases. Therefore, the problem of the reduction in the handling amount of charge caused by the signal propagation systems of the clock pulses φV1A, φV1B and φV1C of the first phase does not occur. However, since the clock pulse of the first phase is divided multiple in the two-dimensional image sensor 190, the number of the vertical transfer signal lines 116A-1, 116B-1 and 116C-1 is increased according to it. This therefore leads to a problem that the ratio of the area occupied by the vertical transfer signal lines relative to the area of the imaging area 118 is increased and the chip area is increased. The increase in the chip area, which directly leads to an increase in the chip cost, is therefore a serious problem.